Sample Resumes

Sample Hardware Engineer Resume

 Objective:

To work in Napa, Solano, or nearby communities in a creative and technically challenging environment where my design skills can be honed to produce state of the art electronic devices.

Employment History:

Aptina LLC (aka Micron Technology Inc.) San Jose CA 8/99 to present.  Design Engineer.

·         Acted as flexible coder to aid in time sensitive sensor and module development. Worked on two IPs to further design and migrate code from one chip to another.

·         Using documentation from and by consulting with system architects, created a new group of modules for the purpose of converting CMOS sensor bayer image data to RGB color space. Included Verilog RTL, documentation, and tests. Also worked with verification engineers and system modelers to validate RTL against Matlab models. Modules included algorithms for kernel generation, noise reduction, image sharpening, defect correction and demosaic.

·         Reverse engineered and recoded various Verilog and VHDL modules from another design group for the purpose of understanding and documenting functionality and for code cleanup.

·         Created Matlab models for simplified color pipeline modules for the purpose of creating test environments. Worked with various Design and Verification Engineers to create debug and test environment.

·         Assisted a software engineer in creating a software controlled emulation system for ASIC verification. This system used C, Matlab and other models to verify synthesized RTL on an FPGA.

·         Designed a system flow in cshell and an home brewed environment for generating an prototype FPGA for ASICs written in mixed VHDL and Verilog. Extensive (read 'painful') experience with Synplify Pro and Xilinx softwares.

·         Designed a simple FPGA DRAM based frame buffer controller using VHDL and Synplify. It was later converted to Verilog by another engineer under my tutelage.

·         Designed three test benches to test module level Verilog Code. Developed a plan and developed both directed and random test to stress the hardware.

Diamond Multimedia, Inc. San Jose CA  8/98 to 8/99.  Senior Hardware Engineer.

·         Acted as hardware middle man on the award winning Viper V770 Project. Some of my responsibilities included: Orcad Schematic capture modification of reference designs provided by NVidia, half of two man team who designed the board layout to be ATX/NLX/AGP 2.0 and AGP 4X compliant, as well as capable of running two banks of 1Mx16 SDRAM with 128 bit wide LVTTL data. Generated bill of material in Agile, for roughly 15 SKUs, using hierarchical sub assembly methodology. Acted as liaison for OEM relations on technical matters. Provided general trouble shooting skills for the debug of OEM board related issues. Worked with various individuals from prototype assembly and QA to sales, marketing, and production, and from the ASIC supplier during the design validation process for release to high volume production.

·         Worked with ASIC designers on the Debug and bring up of a Video Scaler IC. Designed and worked closely with PCB designer to optimize the layout of the high speed data path between the graphics controller and the Video Scaler.

Atari Games, Inc.  Milpitas CA  5/92 to 8/98.  Senior Hardware Engineer.

·         Developed VHDL test bench and source code for an Ultra ATA IDE controller. Targeted Xilinx 4028XL technology. Tested functionality pre and post route using Model Technologies Modelsim.  Tested physical FPGA. Synthesized with Exemplar and Synopsis.

·         Designed the assembly code for a Microchip PIC micro controller to act as a dongle for a software upgrade to existing hardware already in the field.

·         Designed Sony Playstation Coin-Op add in card using Altera 7128E EPLD, Model Technologies V-System, and Synopsys DA and DC. Simulated Sony bus and entire card in a VHDL test bench.

·         Designed and implemented architecture to enhance externally developed ASICS for in house development of Video Games. Design has 64-bit data bus with 104 MB per second peak throughput, up to 8 MB of DRAM and a bank of ping-pong SRAM for faster throughput. Worked extensively with external developer and internal firmware and software developers to isolate painfully tricky bugs within the ASICS. Area 51, Maximum Force and a dual version of both games called the Max A51 Duo Kit shipped.

·         Designed a TI 32C030-40MHz DSP math box board. Design included zero wait state, double banked, ping pong memory for communication to a host processor using CMOS bus switches and fast SRAM. Output was transmitted over an 80 MB / second multi-master token passing bus.  Receiver was asynchronous, masters were synchronous.

·         Designed MC68EC020-25MHz microprocessor “Host board” and aided in the specification for a proprietary bus to interface this board to video and audio subsystems. Design included 54 Macrocell Xilinx EPLD designed in ABEL 5 for address decode, bus control, etc.

·         Implemented two Xilinx FPGA’s using XBLOX and ViewDraw. Parts were XC4005-5, were math intensive (multiple adders, counters and comparators), and were fully simulated using ViewSim to run at greater than 10 MHz.

·         Designed light gun (X,Y) decoder chip that is accurate to within four pixels (2x2) using ViewDraw and an Actel 1010B FPGA. This design shipped in the video game, Area 51 and sequels.

·         Designed hardware including a low cost frame buffer board and a low cost stamp (sprite) based hardware. These designs were modifications of previously designed boards.

·         Wrote documentation for all projects using MS Word, and published them on a local WWW server using Internet Assistant, RTFtoHTML, and recently Front Page 98. Tracked project schedules with MS Project.

Sigma Designs, Inc.  Fremont CA  8/90 to 4/92. Hardware Engineer.

Designed high resolution, monochrome video graphic cards. Designed high frequency clocks (216.667 MHz ECL) and video paths. Learned techniques for debugging and trouble-shooting designs and for designing boards to pass FCC Class-B radiated limits within a PC chassis.

Education:

University of Pittsburgh. B.S. in Electrical Engineering, April 1990

Experience:

Programming Languages - VHDL; Verilog; Rave; C; C++; GNU tools; Abel; Pascal; Basic; 6800, 680X0, 6502 assembly. Experience with perl, cshell, bash.

Operating Systems- Windows; SunOS; Linux.

Software Tools – Cadence NC, SimVision; Verdi; Exemplar; Synopsys; Hyperlynx; ViewLogic ViewDraw, ViewSim; Orcad; Pads; Agile; Xilinx; Altera; Synario; Model Technologies; MS Project; MS Word; MS Excel; MS Powerpoint.

Hardware Tools – HP Infinium; HP 16550C with 4 gsamp / sec active probes; HP 1660; VOMs; component testers; soldering irons, etc.

References: Available upon request