NAVEEN NARAHARISETTI

23754 W.Warren St, Apt #3 Mobile: (734) 716-5412

Dearborn Heights MI-48127. Email:nnaveen@umd.umich.edu

OBJECTIVE Seeking Full-time job as an ASIC Design Engineer.

EDUCATION University of Michigan Dearborn, MI

M.S. in Electrical Engineering

G.P.A. – 4.0 /4.0 Graduation Date: Dec 2008

• VLSI Design • Mod and Des of Electronic Cir & Sys • Active Filter Design • Digital Signal Processing • Computer Networks • Assembly Language Programming on Motorola-HC11• Communication Theory • UWB

Bapatla Engineering College-Acharya Nagarjuna University (India)

B.Tech. in Electronics and Communications Engineering

Percentage: 81.6% Aug 2001-Aug 2005

• Introduction to VLSI • Digital Circuits • Electronic Circuits • Circuit Analysis • Linear Integrated Circuits • Analog and Digital Communications • Communication Systems • Digital Signal Processing • Digital Image Processing

PROFESSIONAL UCSC and Cadence Design Systems

TRAINING Certificate program in VLSI Design Engineering, Specializing in Layout Design Apr 08 – Sep 08

• Introduction to VLSI and ASIC • Introduction to IC Manufacturing • Logic Synthesis • Static Timing Analysis • Advanced ASIC Physical Design • System Integrity in SoC Designs • DFT concepts

CADENCE TOOLS USED:

• RTL Compiler and CTE • SoC Encounter • NanoRoute • Celtic and VStorm • Virtuoso LE • Assura.

AWARD Graduate Merit Scholarship, University Of Michigan Apr 07 - Dec 08

WORK Infor Global Solutions Apr 06 – Apr 07

EXPERIENCE Associate Software Engineer

Product: Interaction Advisor-CRM

Project Description: This product is related to Inbound Marketing of CRM.

Responsibilities:

• Solving Defects related to RT-Studio which was developed using VC++

• Adding new features to RT-Studio.

• Integration of changes made in RT-Studio to IA-Manager.

PROJECTS

STANDARD CELL LAYOUT DESIGNING:

Objective : Standard Cell Layout Designing

Technology : 0.13 micron (TSMC)

Tool Used : Virtuoso Layout Editor, Assura.

Cells Designed : INVXL, NAND2X1, NOR2XL, XOR3X2, OAI33X1, TLATX1, EDFFHQX4, SMDFFHQX2

Responsibilities : Prepared the Stick Diagrams from Spice Net list, drawing Layout from Stick diagrams using Virtuoso Layout Editor, Verifying DRC and LVS.

Physical Design of Full Chip (PCI and DTMF) and Block level (USB):

Responsibilities:

Data Preparation, Floor Planning, Power Planning, Placement, Trial Route, RC Extraction, Static Timing Analysis, IPO, CTS, Adding Filler cells, Detailed Route, GDS-II, DRC and LVS

FULL CHIP:

Title : PERIPHERAL COMPONENT INTERCONNECT.

Tools : SOC Encounter.

Type of design : Flat

Gate count : 1, 24,500

Blocks /Cells / IOs : 12/26640/120

No. of Clocks : 12

Frequency : 150 MHz

Technology : UMC 0.18 micron

FULL CHIP:

Title : DUAL TONE MULTI FREQUENCY CHIP.

Tools : SOC Encounter

Type of design : Flat

Gate count : 42,250

Blocks /Cells /IOs : 4/8260/70

Frequency : 67 MHz

Technology : TSMC 0.18 micron

BLOCK:

Title : UNIVERSAL SERIAL BUS.

Objective : Timing Driven Layout

Tools : SOC Encounter, Common Timing Engine.

Gate count/Area : 1, 84,364/ 938820.2 um^2

Macros /STD Cells/ : 5/41835

Frequency : 50MHz

Technology/Layers : TSMC 0.13 micron/5 Metal Layers

AES (Advanced Encryption Standard-Cryptography)

Senior Year Bachelors Degree Project June 04-June 05

Project Description: Implementation of AES algorithm using VHDL on Xilinx Spartan-3 kit.

• Responsible for the integration of all the modules and release of the project.

• Implemented the algorithm in VHDL and reported the functions of AES to guide.

• Responsible for implementation and proper functioning of the modules such as CIPHER (converts plain text to cipher text), INVERSE CIPHER (converts cipher text to plain text) and KEY EXPANSION (generates a series of round keys from cipher key.

COMPUTER L-Edit, MATLAB, PSpice, Verilog,Tcl, C, C++, VC++, HTML, Microsoft Office.

SKILLS

DATA BASE MS-SQL, PL-SQL